1. Field of the Invention
This invention relates to digital processing systems and more particularly to digital processing systems containing self-test circuitry.
2. Description of the Prior Art
Ever since the introduction of the integrated circuit, the functions implemented by integrated circuits have become more and more complex. In the early days of integrated circuits, testing the performance of an integrated circuit was fairly simple and straightforward. However, as the integrated circuits became more complex, the testing of the integrity of circuitry contained in the integrated circuit has become more difficult and time consuming. The introduction of the microprocessor and microcomputer with read-only memory for the storage of instructions and data together with complex arithmetic circuitry has necessitated the requirement for integrated circuits to include circuitry to aid in the testing of the integrated circuit itself. Since this integrated circuit testing is not only required during the manufacture of the integrated circuit itself, but also in the field to determine if the part is still functioning correctly. Systems involved in testing complex integrated circuits can be quite costly and the tests themselves can be quite time consuming. Integrated circuits containing circuitry to assist in these tests can provide a savings in time and expense. An example of a microprocessor with such a self-test feature is illustrated in U.S. Pat. No. 4,158,431 entitled "Self-Test Feature for Appliances or Electronic Devices Operated by Microprocessor" by Michael G. Bavel and Allen J. Shannon, assigned to Texas Instruments Incorporated.
This invention uses a technique known in the prior art. This technique is called checksumming and involves adding the contents of memory to arrive at a total that is then compared to a number stored in memory which represents what this sum should be. The checksum test not only determines the validity of the contents that makes up the sum test, but also determines the correct operation of the circuitry used in adding the numbers to arrive at this sum. When the contents of the memory to be summed consist of words of equal length to the parallel arithmetic logic unit width, the checksum operation is fairly straightforward. If, however, the width of the parallel arithmetic logic unit is different than the width of the instruction words, then the checksum operation becomes difficult.
The object of this invention is to provide a self-test circuit that includes the ability to perform checksum operations on the memory of one binary digit width with a parallel arithmetic logic unit of a different binary digit width.